Tester Capabilities

Testing IC’s for Space

Radiation Test Challenges for IC’s and Semiconductor components

Space Radiation
(with regards to electronics)

  • Charged Particles (ionizing radiation)
  • Gamma Radiation (ionizing electromagnetic radiation)
  • Heavy Ions, protons, neutrons,
  • Gamma, (gamma-dot)

Single Charged Particles

Single Event Effects (SEE)

  • state upsets
    Memory / Latches / stated logic (flip flops..)
  • transient outputs
    Regulators / OpAmps / DACs / Power FETs

Single Event Latchups (SEL)

  • permanent high current state
    All CMOS – parasitic SCR
  • Single Event Gate Rupture (SEGR)
    Power FETs

Single Event Functional Interrupts (SEFI)

  • Permanent change in operation
    requiring reset

Total Ionizing Dose

Gamma Radiation

Increased currents

  • Parasitic/edge leakage
    IDD / pin ILeakage[I,O]
  • Voltage Threshold Shifts

Circuit Changes (plethora)

  • Bias
  • Regulation
  • FET I/V characteristics
  • Logic Levels

Functional Failure

Analog Parts

  • Extremely Low Dose Rate Sensitivity (ELDRS)
    increased component degradation with decreasing TID dose rate
    Bipolar technologies

Transient Dose

Gamma Dot

  • Logic/Memory Upset
  • Transient Output
    e.g. logic high droop
  • Transient Idd pulse
    may be amps
  • Survivability
    burnout

Neutron Damage

All bipolar analog circuits will degrade

OpAmps, Comparators, Power Circuits

Bipolar transistor

  • Gain degradation
  • Lower breakdown voltage
  • Increase leakage
  • burnout

Flying Electronics In Space

1. Begins with knowing part RAD behavior

2. Design a system that tolerates/accommodates part’s RAD behavior

Hardened ICs vs COTS (Commercial Off-The-Shelf)

  • Hardened
    ICs have foundry solutions to mitigate Rad effects
    ex. MRAD TID vs a few KRAD for COTs
    ex. Upset mitigation, prevention
    limited types, expensive
  • COTS – inexpensive, higher technology

COTS: What to test, what not to

  • Inherently hard ?
  • Existing data ?
  • Expected Environment (earth orbits, deep space)

COTS: Characterization (discover COTS part behavior)

COTS: Qual (Statistical performance of a group, COTS lifetime buys)

Radiation Test Facilities

  • Large / Remote
    Travel
    portable test
  • Must protect
    test equipment & test boards from radiation
  • Only irradiate IC

JDi Tester Solves Radiation Test Challenges

1. Distance

DUT must be separated from tester (ft – 10’s ft – 100 ft)

2. Concurrent RAD effects – must unravel

SEFI might mask underlying SEUs,
SEFI might masquerade as micro latch

3. FULL Test (ac, DC – as well as functional)

as challenging as production test
– further complication of RAD environments

time: TID = max 2hr test interval btwn rad exposures (MIL STD 883)
rapid anneal: minutes – in-situ testing

4. Latchup

detect, protect

5. Test Head / DUT board electronics

protect from radiation- isolate

6. Large Universe of Part Types

7. Travel to remote facilities

8. Real Time Results

beam time – expensive :
must know you’re getting good data

Example – How JDi Tester solves Radiation Test Challenges

DISTANCE

SEE, LINAC: 10s ft

TID, Neutron, Proton: 10 – 30+ ft

CERN CHARM or Reactor: 100 ft

Production IC Testers — Not Suitable —
( they require inches of separation)

“Distance” must be “Designed In” to tester

Requires pipeline architecture –

  • multiple signals in cabling at once
    separation in time for compare
  • needs transmission line technology (50 ohm)
    separate I & O lines

Most DUTs can’t drive long lines

  • remote return drivers