ATV Digital Test
The Algorithmic Test Vector (ATV) system is a low-cost, portable, high performance digital tester which represents a major advance and simplification in the art of integrated circuit testing. Its modular architecture and custom ASICs achieve dramatic miniaturization and flexibility while delivering performance found in console systems costing many times as much.
Simple Test Development
With ATV, test development is broken into three separate elements, organized the natural way engineers work with parts:
- Timing Diagrams
- Pin Assignments
- Test Programs (Algorithms)
Each of these elements are created and stored separately, then combined at run time. Dynamic combinations allow simple yet powerful test variations. A new part can be tested by merely creating a new package description. Speed enhancements for next generation parts only require new timing diagrams. A single test program can be used for an entire family of parts in various packages (Note: this is used extensively in the JDi Test Sets, above). Due to this modularity, dramatically fewer programming elements need to be maintained in your archive. Productivity is enhanced since new tests are assembled using existing pin/package, timing and test program building blocks.
Each ATV pin has independent timing and can store up to 7 timing sets which are selectable on-the-fly. Timing is specified by graphically creating timing diagrams visually similar to the ones found in part specification sheets. Waveforms in each timing diagram are assigned pin/pin group names that are also used in part/package description and test programs. Example waveforms might include ADDR, DATA, RW*, CE*, etc., where ADDR represents a group of pins and RW* represents a single strobe pin.
ATV formats include NRZ, Return to One, Return to Zero or Return to Complement. Timing diagrams can be as short as 20nS and edges placed with 200 pS resolution.
Interconnections between the tester and DUT are specified graphically. Pins or groups of pins are selected and assigned names from a pull-down list derived from a timing diagram set.
Test Programs (Algorithms)
Test vectors can be imported from ASCII files or they can be generated “real time” algorithmically. Algorithmic generation is powerful because millions of vectors can be generated from a few lines of code. This is especially important when testing memories or devices containing memory blocks.
Imported vectors are essential when testing complex devices such as ASICs.
With ATV, imported vectors and algorithmic generation can be combined to capture the best of both approaches. This can be important when testing SOC (System on a Chip) technologies.
ATV test vector algorithms are programmed in a simple integrated editor. These algorithms are compiled into high speed binaries which are downloaded to the ATV tester. The source language includes subroutines and interrupts. Procedure libraries are also implemented so test algorithms can be simply built by including existing common code.
An extensive library filled with working examples for many part families is included with the installation of the JDi software.
Fast Hardware Loop
ATV provides a hardware feature which repeats a section of test vector code without the time penalty normally associated with software loops. With this feature, ATV can algorithmically generate 40 million timing diagrams per second using loop constructs. (See loop, in the above algorithm code snippet.)
ATV uses a synchronized timing architecture and distributed processing so systems can be expanded to over 500 pins
Base Digital Tester – 62 pins
(32 I/O – 30 Out Only)
Add I/O cards – 16 I/O per Card
Add Output Cards – 24 Outs per Card
Expand………………….to over 350 pins
Test System Cards
A system is comprised of a Test Vector Processor (TVP) card, clock generator, and some mixture of 16-channel I/O, and 24-channel Address/Output Only cards.
- TVP Card – The TVP card controls algorithmic program flow for the entire system. It also has a programmable power supply which measures IDDQ currents, 6 output strobe lines, trigger-in and trigger-out controls.
- I/O Cards – I/O cards have 16 input and output lines which can be used as I/O pairs or separately.
- Address/Output Cards – Address/Output cards have 24 channels.
On I/O or Address cards, some or all of the output channels can be assigned to an ax counter which can be initialized, incremented and decremented. The ax counter has an arithmetic logic unit which can generate complex address sequences on-the-fly. Output pins can be multiplexed for testing segmented address devices such as RAS/CAS on DRAMs.
Using ATV, it is not necessary to have the large electronic test heads and associated mechanical manipulators prevalent in most test environments.
Digital Tester Features – ATV
- Trig In / Trig Out
- Vdd w/ Current Limit, Idd meas, Lathcup detection
- 6 Output Only Strobes
- DC Parametrics – 1 SMU I/V source measure
- 16 I/O pairs, ALU ax register for pattern math
Output Only Cards
- 16 I/O pairs, ALU ax register for pattern math
- Expandable (15, 30 Slot chassis’s)
- Separate DUT from Tester ( > 100 feet)
- Can test over coaxial cables
- Format-able Drives – RTRN0, RTRN1, RTRNC, NRZ
- Variable Output Range : 0 to 5.5 v
- 50 ohm Reverse Terminated Drivers
- Separate Compare Levels (VCmpH, VCmpL – variable range)
ATV keeps most of the active electronics in the tester, and connections to the DUT can be as simple as a cable set. For general testing, the system includes a simple test head that provides an easy interface between DUT cards and system cables. The test head has built-in analog buffer drivers for maximum test speeds.
The test head accepts daughter boards which are customized to specific part types and packages. ATV comes with multi-functional daughter boards which can accept one to three parts, in package types of 300 and 600 mil DIP’s and PGA’s. Surface mount parts can be used on these daughter boards by mounting them on commercially available DIP adapter boards. Also, the user can make custom daughter boards to insert into the test head.
Programmable Thevinin Load
ATV I/O channels have three programmable drive conditions, all of which are asserted on-the-fly as specified in the timing diagrams. Logic high and logic low are used when sending data to the DUT. The third drive condition, reverse terminate, is used to develop a programmable Thevinin load when the DUT is outputting a signal. A Thevinin load consists of a series resistance back terminated in a voltage source. The reverse terminate drive establishes the voltage source for the load and resistors on the DUT card provide the series resistance.